1. Field of the Invention
The present invention relates to an active pixel sensor cell and, more particularly, to an active pixel sensor cell that reduces noise in the photo information extracted from the cell.
2. Description of the Related Art
Charge-coupled devices (CCDs) have been the mainstay of conventional imaging circuits for converting a pixel of light energy into an electrical signal that represents the intensity of the light energy. In general, CCDs utilize a photogate to convert the light energy into an electrical charge, and a series of electrodes to transfer the charge collected at the photogate to an output sense node.
Although CCDs have many strengths, which include a high sensitivity and fill-factor, CCDs also suffer from a number of weaknesses. Most notable among these weaknesses, which include limited readout rates and dynamic range limitations, is the difficulty in integrating CCDs with CMOS-based microprocessors.
To overcome the limitations of CCD-based imaging circuits, more recent imaging circuits use active pixel sensor cells to convert a pixel of light energy into an electrical signal. With active pixel sensor cells, a conventional photodiode is typically combined with a number of active transistors which, in addition to forming an electrical signal, provide amplification, readout control, and reset control.
FIG. 1 shows an example of a conventional CMOS active pixel sensor cell 10. As shown in FIG. 1, cell 10 includes a photodiode 12 connected to a first intermediate node N.sub.IM1, and a reset transistor 14 that has a drain connected to a power supply node N.sub.PS, a source connected to node N.sub.IM1, and a gate connected to a first input node N.sub.IN1.
Cell 10 further includes a buffer transistor 16 and a row select transistor 18. Buffer transistor 16 has a drain connected to node N.sub.PS, a source connected to a second intermediate node N.sub.IM2, and a gate connected to node N.sub.IM1, while row select transistor 18 has a drain connected to node N.sub.IM2, a source connected to a third intermediate node N.sub.IM3, and a gate connected to a second input node N.sub.IN2.
In addition, a detection and calculation circuit 20 is connected to the third intermediate node N.sub.IM3. As further shown in FIG. 1, circuit 20 includes a latch/column sense amplifier 22 and a current mirror 24 which provides the necessary load for reading out the cells. Current mirror 24 must sink a fairly small current in order to minimize fixed pattern noise that results from mismatches in the channel lengths of the buffer transistors when cell 10 is incorporated into an array of cells 10.
FIGS. 2A-2C show timing diagrams that illustrate the operation of cell 10. As shown in FIGS. 1 and 2A-2C, the operation of cell 10 begins by briefly pulsing the gate of reset transistor 14 with a reset voltage V.sub.RESET at time t.sub.1. The reset voltage V.sub.RESET, which is equal to Vcc (+5V), resets the voltage on photodiode 12 to an initial integration voltage to begin an image collection cycle.
At this point, the initial integration voltage on photodiode 12 (the first intermediate node N.sub.IM1) is defined by the equation V.sub.RESET -V.sub.T14 -V.sub.CLOCK, where V.sub.T14 represents the threshold voltage of reset transistor 14, and V.sub.CLOCK represents reset noise from the pulsed reset voltage (assumed to be constant). Similarly, the initial integration voltage on the second intermediate node N.sub.IM2 is defined by the equation V.sub.RESET -V.sub.T14 -V.sub.CLOCK -V.sub.T16, where V.sub.T16 represents the threshold voltage of buffer transistor 16 (functioning as a source follower).
After the reset voltage V.sub.RESET has been pulsed and the voltage on photodiode 12 (the first intermediate node N.sub.IM1) has been reset, a row select voltage V.sub.RS is applied to the second input node N.sub.IN2 at a time t.sub.2 which immediately follows the falling edge of the reset pulse V.sub.RESET. The row select voltage V.sub.RS causes the voltage on the second intermediate node N.sub.IM2, which represents the initial integration voltage of the cycle, to appear on the third intermediate node N.sub.IM3. Detection and calculation circuit 20 then amplifies, digitizes, and stores the value of the initial integration voltage as it appears on the third intermediate node N.sub.IM3.
Next, from time t.sub.2, which represents the beginning of the image collection cycle, to a time t.sub.3, which represents the end of the image collection cycle, light energy, in the form of photons, strikes photodiode 12, thereby creating a number of electron-hole pairs. Photodiode 12 is designed to limit recombination between the newly formed electron-hole pairs.
As a result, the photogenerated holes are attracted to the ground terminal of photodiode 12, while the photogenerated electrons are attracted to the positive terminal of photodiode 12 where each additional electron reduces the voltage on photodiode 12 (the first intermediate node N.sub.IM1). Thus, at the end of the image collection cycle, a final integration voltage will be present on photodiode 12 (the first intermediate node N.sub.IM1).
At this point (time t.sub.3), the final integration voltage on photodiode 12 (the first intermediate node N.sub.IM1) is defined by the equation V.sub.RESET -V.sub.T14 -V.sub.CLOCK -V.sub.S, where V.sub.S represents the change in voltage due to the absorbed photons. Similarly, the final integration voltage on the second intermediate node N.sub.IM2 is defined by the equation V.sub.RESET -V.sub.T14 -V.sub.CLOCK -V.sub.T16 -V.sub.S.
At the end of the image collection cycle (time t.sub.3), the row select voltage V.sub.RS is again applied to the second input node N.sub.IN2. The row select voltage V.sub.RS causes the voltage on the second intermediate node N.sub.IM2, which represents the final integration voltage of the cycle, to appear on the third intermediate node N.sub.IM3. Detection and calculation circuit 20 then amplifies and digitizes the value of the final integration voltage as it appears on the third intermediate node N.sub.IM3.
Following this, detection and calculation circuit 20 determines the number of photons that have been collected during the integration cycle by calculating the difference in voltage between the digitized final integration voltage taken at time t.sub.3 and the digitized stored initial integration voltage taken at time t.sub.2. At this point, the difference is voltage is defined by the equation (V.sub.RESET -V.sub.T14 -V.sub.CLOCK -V.sub.T16)-(V.sub.RESET -V.sub.T14 -V.sub.CLOCK -V.sub.T16 -V.sub.S), thereby yielding the value V.sub.S.
Once the final integration voltage has been latched by detection and calculation circuit 20, the reset voltage V.sub.RESET is again applied to the first input node N.sub.IN1 at time t.sub.4, which immediately follows the rising edge of the row select voltage V.sub.RS at time t.sub.3. The reset voltage V.sub.RESET again resets the voltage on photodiode 12 to begin another image collection cycle.
One of the problems with active pixel sensor cell 10, however, is that the reset voltage V.sub.RESET and the row select voltage V.sub.RS have periods, both of which are approximately 30 mS, which are sufficiently long enough to introduce a substantial amount of 1/f noise into the cell. 1/f noise, which results from the trapping and de-trapping of surface charges, can be accurately modeled as variations in the threshold voltages of the reset and buffer transistors 14 and 16.
As a result, the number of photons which are absorbed by photodiode 12 during an image collection period is more properly defined by the equation (V.sub.RESET -V.sub.T14 -V.sub.CLOCK -V.sub.T16)-(V.sub.RESET -V.sub.T14 -V.sub.CLOCK -V.sub.T16 -V.sub.S -V.sub..alpha.), where V.sub..alpha. represents the variations in the threshold voltages of transistors 14 and 16 due to 1/f noise.
Thus, the variations in the threshold voltages of the reset and buffer transistors 14 and 16 add an error term V.sub..alpha. which erroneously yields V.sub.S +V.sub..alpha. as the number of absorbed photons, thereby limiting the accuracy of the cell.
To eliminate the introduction of 1/f noise that results from variations in the threshold voltage of reset transistor 14, a first method of operating cell 10 was disclosed in the parent application where the voltage on the photodiode of the cell was reset to the power supply voltage by utilizing a reset voltage which is greater than the power supply voltage by at least one threshold voltage.
In addition, to further reduce the introduction of 1/f noise, a second method of operating cell 10 was disclosed in the parent application where the cell was read immediately before and after the cell was reset.
Experimental results, however, have indicated that when no signal is present, i.e., when cell 10 is not exposed to a light source, and cell 10 is reset and read according to the method of the parent invention, the voltages read from the third intermediate node N.sub.IM3, which should be the same, include noise which causes the voltages to differ by tens of millivolts. Thus, there is a need for an active pixel sensor cell and a method for operating the cell which reduces the introduction of this noise.